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1. uart-controlled-system-with-multi-clock-domain uart-controlled-system-with-multi-clock-domain Public

   Digital backend flow for a UART-controlled multi-clock-domain system (SYS_TOP): synthesis, scan-chain DFT insertion, and Formality equivalence checking for a 50 MHz / 3.6864 MHz design.

   Verilog 2

2. TinyNPU4 TinyNPU4 Public

   Tiny Tapeout INT4 neural-network accelerator (64-4-1) that classifies 8x8 grayscale images as Cat or Dog, with dual MAC lanes and a Cocotb testbench.

   Python 4 5

3. scientific-project-council scientific-project-council Public

   Forked from faroukahmed89-droid/claude-council-khalifa

   The council ⚖️ evaluates university, PBL, seminar, graduation, engineering, research-prototype, and interdisciplinary projects. It challenges scientific weakness, unrealistic scope, unavailable res…

   Python 1

4. UART_TX UART_TX Public

   Verilog UART transmitter with FSM-based framing, configurable even/odd parity, testbench, and SpyGlass lint sign-off.

   Verilog 2 1

5. 16-bit-ALU 16-bit-ALU Public

   Modular 16-bit ALU in Verilog with a central opcode decoder driving arithmetic, logic, compare, and shift units. Includes a 28-case self-checking testbench and SpyGlass lint sign-off.

   Verilog 2 1