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Fix double-wide OEB and the conb_1 LVS property mismatch - #120
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… double-wide wrapper)
sky130_fd_sc_hd__conb_1's (and sky130_fd_sc_hvl__conb_1's) antenna-protection res_generic_po resistor has a documented upstream spice-vs-layout mismatch: the bundled spice model declares l=0.5, but the cell's actual drawn geometry is l=0.045 (see google/skywater-pdk#276). Netgen's default 1% length tolerance turns this stale-model artifact into a hard LVS property mismatch ('Error: Property mismatch.') on an unmodified, standard PDK cell, even when the circuits otherwise match uniquely. res_generic_po is described by the tool's own author as 'more of a symbolic layer used to separate nodes for LVS rather than an actual simulatable device,' so dropping the length comparison for this one device (w stays compared) is a safe, targeted fix -- it does not touch tolerance rules for any other resistor device type (res_high_po, res_xhigh_po, etc.).
d-m-bailey
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Oct 28, 2026
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@marwaneltoukhy The discrepancy in the conb_1 size comes from a mismatch between the spice and gds files in the PDK.
The user is probably using an older version of the gds.
I would not recommend removing the length check because and outdated gds is being used.
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Branch double-wide-production-ready from the double-wide production-ready work. See chipfoundry/double-wide-env PR 1 for the full set.