openlane

ASIC implementation flow infrastructure, successor to OpenLane

The next generation of OpenLane, rewritten from scratch with a modular architecture

Open source compliance automation for SOC 2, GDPR, ISO27001, NIST 800-53, and more

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs

A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out

tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles

the openlane ui - holds the openlane console

AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

Gate-level visualization generator for SKY130-based chip designs.

This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.